This invention generally relates to integrated circuits and methods of fabrication. More particularly, the present invention relates to back end of the line (BEOL) interconnect structures and methods of forming airgaps between metal lines using a sidewall image transfer process such as a self-aligned double patterning (SADP) process.
Typical integrated circuits are formed by first fabricating individual semiconductor devices using processes referred to generally as the front end of line (FEOL). Thereafter, the individual devices on the integrated circuit are interconnected by forming the wiring of the wafer using processes referred to generally as the back end of line (BEOL). In the BEOL, the individual devices (transistors, capacitors, resistors, etc.) are interconnected with interconnects and a metallization layer, which function as the wiring network of the wafer. Common metals that are used to form the metallization layers and interconnects are copper, cobalt, tungsten, and aluminum. BEOL generally begins when the first layer of metal (MO) is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. Double patterning processes such as self-aligned double patterning (SADP) or litho-etch-litho etch (LELE) are typically part of the BEOL process for advanced design rules.